Scaling of semiconductor based memory technologies such as SRAM, DRAM, Flash etc. is near its fundamental limit and magnetic random access memory (MRAM) is one technology which has been considered a potential candidate for replacement, as MRAM offers virtually unlimited endurance and lower write time. Various MRAM architectures use a magnetic tunnel junction (MTJ) as the memory element and rely on high tunneling magnetoresistance (TMR) for reading operation. Fabrication of high quality MTJs depends on the quality of the tunneling barrier, as its thickness determines the life time and TMR. Pinholes and other defects during the formation of the dielectric layer degrades the TMR and breakdown tolerance. Moreover, MTJs, when integrated with standard back-end-of-line (BEOL) CMOS processing, may be subject to over-annealing as the optimum annealing temperature of MTJ is much lower than the standard CMOS BEOL temperature. Over-annealing causes various issues such as creation of a dead layer, lattice mismatch between the magnetic and the oxide layer etc. The large variation of TMR and reliability issues induced by such process variation creates challenges in realizing high bit density MRAM arrays. Thus, improvements are needed in the field. The NMS may be either a single ferromagnetic layer or a plurality of magnetically exchange coupled layers whose magnetic interactions are controlled by judicious coupling interlayers in order to provide the desired magnetic properties (magnetization, anisotropy and coercivity) to optimize switching.